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#	Item
561	NDC: Analyzing the Impact of 3D-Stacked Memory+Logic Devices on MapReduce Workloads Seth H Pugsley1, Jeffrey Jestes1, Huihui Zhang1 , Rajeev Balasubramonian1 , Vijayalakshmi Srinivasan2, Alper Buyuktosunoglu2, Al Davis1 Add to Reading List Source URL: www.cs.utah.edu Language: English - Date: 2014-02-09 01:02:50 Parallel computing Electronics Blue Gene Multi-core processor MapReduce AMD 10h Dynamic random-access memory CPU cache Computer data storage Computer memory Computing Computer hardware
562	Part C Instruction scheduling Instruction scheduling character stream token stream Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2006-03-07 06:00:00 Central processing unit Compiler optimizations Hazard Instruction set Instruction scheduling CPU cache Cycles per instruction Instruction pipeline Computer architecture Computer hardware Computing
563	A Tuning Framework for Software-Managed Memory Hierarchies Manman Ren Stanford University Add to Reading List Source URL: theory.stanford.edu Language: English - Date: 2008-09-16 13:24:23 Cache Computer performance Software optimization Cell CPU cache Lookup table Loop fusion Reuse Program optimization Computing Compiler optimizations Computer architecture
564	SH-X3 Flexible SuperH Multi-core for High-performance and Low-power Embedded Systems 1 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:59:21 Cache coherency Instruction set architectures Embedded microprocessors Microcontrollers SuperH MESI protocol CPU cache Central processing unit Bus sniffing Computer hardware Computing Computer architecture
565	HC19TRIPS- A Distributed Explicit Data Graph Execution (EDGE) Microprocessor.ppt Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:59:05 Computer memory Explicit Data Graph Execution CPU cache Cell Microprocessors Scratchpad memory Direct memory access TRIPS architecture Computer hardware Computer architecture Computer engineering
566	Microsoft PowerPoint - 5_marr [Read-Only] Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:40:18 Hyper-threading Threads X86 architecture NetBurst Xeon Symmetric multiprocessing Intel CPU cache Tejas and Jayhawk Computer hardware Computing Computer architecture
567	Weaving Relations for Cache Performance Anastassia Ailamaki ‡ Carnegie Mellon University David J. DeWitt Add to Reading List Source URL: research.cs.wisc.edu Language: English - Date: 2001-06-09 13:12:00 Data Database management systems Cache CPU cache Central processing unit Computer memory Relational database PaX Tar Data management Computing Database theory
568	Copyright © SuperSpeed LLC All Rights Reserved. 09 June 2011 QUICK REFERENCE FOR SUPERCACHE SERVER EDITION Add to Reading List Source URL: www.superspeed.com Language: English - Date: 2012-11-12 13:58:26 Cache Software Memory management CPU cache Central processing unit Paging Web cache Non-Uniform Memory Access Windows Server Computing Computer memory Computer hardware
569	Using Synology SSD Technology to Enhance System Performance Synology Inc. Table of Contents Add to Reading List Source URL: ukdl.synology.com Language: English - Date: 2014-12-08 21:49:23 Computer performance Data transmission IOPS Solid-state drive CPU cache Smart Response Technology RAID Synology VRPM Computer hardware Computing Cache
570	Scientic Computing with GPUs Part 6: memory access optimisations Dominik Göddeke and Robert Strzodka Faculty of Mathematics Applied Mathematics and Numerics Add to Reading List Source URL: gpgpu.org Language: English - Date: 2014-08-11 19:25:16 Graphics hardware GPGPU Video cards Nvidia CUDA CPU cache Dynamic random-access memory Random-access memory Graphics processing unit Computer hardware Computing Computer memory

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